_______________ge ne ra l de sc ript ion the max797h high-performance, step-down dc-dcconverter provides main cpu power in battery-powered systems. a 40v rating on the power stages input allows operation with high-cell-count batteries and a wide range of ac adaptors. this buck controller achieves 96% efficiency by using synchronous rectification and maxims proprietary idle mode? control scheme to extend battery life at full-load (up to 10a) and no-loadoutputs. excellent dynamic response corrects output tran- sients caused by the latest dynamic-clock cpus within five300khz clock cycles. unique bootstrap circuitry drives inexpensive n-channel mosfets, reducing system cost and eliminating the crowbar switching currents found in some pmos/nmos switch designs. the max797h has a logic-controlled and synchronizable fixed-frequency, pulse-width-modulating (pwm) operating mode, which reduces noise and rf interference in sensi - tive mobile-communications and pen-entry applications. the skip override input allows automatic switchover to idle-mode operation (for high-efficiency pulse skipping) atlight loads, or forces fixed-frequency mode for lowest noise at all loads. the max797h is pin compatible with the popu - lar max797, but has a higher input voltage range. the max797h comes in a 16-pin narrow so package. ________________________applic a t ions notebook and subnotebook computersindustrial controls ____________________________fe a t ure s ? 96% efficiency ? up to 40v power input ? 2.5v to 6v adjustable output ? preset 3.3v and 5v outputs (at up to 10a) ? 5v linear-regulator output ? precision 2.505v reference output ? automatic bootstrap circuit ? 150khz/300khz fixed-frequency pwm operation ? programmable soft-start ? 375a quiescent current (v in = 12v, v out = 5v) ? 1a shutdown current m ax 7 9 7 h h igh-volt a ge , st e p-dow n cont rolle r w it h sync hronous re c t ifie r for cpu pow e r ________________________________________________________________ maxim integrated products 1 idle mode is a trademark of maxim integrated products. 19-1239; rev 0; 7/97 __________________pin configura t ion 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 dh lx bst dl gnd ref skip ss top view max797h pgnd vl v+ csl csh fb shdn sync so __________typic a l ope ra t ing circ uit max797h shdn dh +3.3v output +4v to +40v power input bst lx dl pgnd csh csl ss ref sync gnd skip fb v+ +4.5v to +30v supply input vl pin-package temp. range part ? 16 narrow so -40c to +85c max797hese for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 for small orders, phone 408-737-7600 ext. 3468. ______________orde ring i nform a t ion ? u downloaded from: http:///
m ax 7 9 7 h h igh-volt a ge , st e p-dow n cont rolle r w it h sync hronous re c t ifie r for cpu pow e r 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0a, t a = 0c to +85c , sync = 0v, unless otherwise noted.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the devi ce. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational s ections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ................................................................-0.3v to 36v gnd to pgnd........................................................................2v vl to gnd...................................................................-0.3v to 7v bst to gnd ..............................................................-0.3v to 46v dh to lx .....................................................-0.3v to (bst + 0.3v) lx to bst ....................................................................-7v to 0.3v shdn to gnd ...........................................................-0.3v to 36v sync, ss, ref, fb, skip , dl to gnd ...........-0.3v to (vl + 0.3v) csh, csl to gnd.......................................................-0.3v to 7v vl short circuit to gnd..............................................momentary ref short circuit to gnd ...........................................continuous vl output current ...............................................................50ma continuous power dissipation (t a = +70 c) so (derate 8.70mw/c above +70 c) ........................696mw operating temperature range max797hese .................................................-40c to +85c storage temperature range .............................-65c to +160c lead temperature (soldering, 10sec) .............................+300c rising edge, hysteresis = 25mv v+ rising edge, hysteresis = 15mv shdn = 2v, 0ma < i vl < 25ma, 5.5v < v+ < 30v csh - csl, negative csh - csl, positive fb = vl, 6v < power input < 40v (note 4) 25mv < (csh - csl) < 80mv 0mv < (csh - csl) < 80mv, fb = vl, 6v < power input < 40v, includes line and load regulation (note 4) external resistor divider csh - csl = 0v 0mv < (csh - csl) < 80mv conditions v 4.2 4.7 vl/csl switchover voltage v 3.8 4.1 vl fault lockout voltage v 4.7 5.3 vl output voltage ma 2.0 ss fault sink current a 2.5 4.0 6.5 ss source current 40 v 4.5 30 input supply range -50 -100 -160 mv 80 100 120 current-limit voltage 1.5 v 4.85 5.10 5.25 5v output voltage (csl) v ref 6 nominal adjustable outputvoltage range v 2.43 2.505 2.57 feedback voltage % 2.5 load regulation units min typ max parameter high-side mosfet drain 0mv < (csh - csl) < 80mv, fb = 0v,4.5v < power input < 40v, includes line and load regulation (note 4) v 3.20 3.35 3.46 3.3v output voltage (csl) fb = 0v, 4.5v < power input < 40v (note 4) %/v 0.04 0.06 line regulation +3.3v and +5v step-down controllers flyback/pwm controller internal regulator and reference 0.04 0.06 downloaded from: http:///
m ax 7 9 7 h h igh-volt a ge , st e p-dow n cont rolle r w it h sync hronous re c t ifie r for cpu pow e r _______________________________________________________________________________________ 3 electrical characteristics (continued)(v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0a, t a = 0c to +85c , sync = 0v, unless otherwise noted.) shdn , 0v or 30v shdn , skip sync sync = 0v or 5v no external load (note 1) sync = ref guaranteed by design csh = csl = 6v v+ = 4v, csl = 0v (note 2) sync = 0v or 5v shdn = 0v, v+ = 30v, csl = 0v or 6v falling edge 0a < i ref < 100a sync = ref shdn = 0v, csl = 6v, v+ = 0v or 30v, vl = 0v conditions 2.0 2.0 v vl - 0.5 input high voltage % 93 96 89 91 maximum duty factor khz 190 340 oscillator sync range ns 200 sync rise/fall time ns 200 sync low pulse width ns 200 sync high pulse width 125 150 175 khz 270 300 330 oscillator frequency 2.45 2.505 2.55 v reference output voltage mw 4.8 6.6 quiescent power consumption mw 4 8 dropout power consumption 1 5 a v+ shutdown current v 1.8 2.3 reference fault lockout voltage mv 50 reference load regulation a 0.1 1 csl shutdown leakage current units min typ max parameter fb = csh = csl = 6v, vl switched over to csl 1 5 a v+ off-state leakage current dl forced to 2v fb, fb = ref csh, csl, csh = csl = 4v, device not shut down sync, skip a 1 dl sink/source current 100 50 1.0 shdn , skip sync 0.5 v 0.8 input low voltage dh forced to 2v, bst - lx = 4.5v a 1 dh sink/source current high or low, bst - lx = 4.5v high or low 7 dh on-resistance 7 dl on-resistance oscillator and inputs/outputs na input current a downloaded from: http:///
%/v m ax 7 9 7 h h igh-volt a ge , st e p-dow n cont rolle r w it h sync hronous re c t ifie r for cpu pow e r 4 _______________________________________________________________________________________ electrical characteristics (continued)(v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0a, t a = -40 to +85c , sync = 0v, unless otherwise noted.) (note 3) note 1: since the reference uses vl as its supply, v+ line-regulation error is insignificant. note 2: at very low input voltages, quiescent supply current can increase due to excess pnp base current in the vl linear regulator. this occurs only if v+ falls below the preset vl regulation point (5v nominal). note 3: all -40c to +85c specifications are guaranteed by design. note 4: the power input is the high-side mosfet drain. external resistor divider 0mv < (csh - csl) < 80mv, fb = 0v, 4.5v < power input < 40v, includes line and load regulation (note 4) v+ 0mv < (csh - csl) < 80mv, fb = vl, 6v < power input < 40v, includes line and load regulation (note 4) conditions v ref 6.0 nominal adjustable outputvoltage range v 3.10 3.35 3.56 3.3v output voltage (csl) 5.0 30 v 4.70 5.10 5.40 5v output voltage (csl) units min typ max parameter csh - csl, negative csh - csl = 0v fb = vl, 6v < power input < 40v (note 4) csh - csl, positive -40 -100 -160 current-limit voltage v 2.40 2.60 feedback voltage 0.04 0.06 mv 70 130 fb = csh = csl = 6v, vl switched over to csl shdn = 0v, v+ = 30v, csl = 0v or 6v rising edge, hysteresis = 25mv no external load (note 1) 0a < i ref < 100a a 1 10 v+ off-state leakage current a 1 10 v+ shutdown current v rising edge, hysteresis = 15mv shdn = 2v, 0ma < i vl < 25ma, 5.5v < v+ < 30v 4.2 4.7 vl/csl switchover voltage v 2.43 2.505 2.57 reference output voltage mv 50 reference load regulation v 3.75 4.15 vl fault lockout voltage v 4.7 5.3 vl output voltage sync = ref sync = 0v or 5v 89 91 khz 210 320 oscillator sync range khz sync = ref 120 150 180 oscillator frequency ns 250 sync high pulse width ns csh = csl = 6v 250 sync low pulse width 250 300 350 mw 4.8 8.4 quiescent power consumption high or low, bst - lx = 4.5v high or low sync = 0v or 5v 7 dh on-resistance 7 dl on-resistance % 93 96 maximum duty factor high-side mosfet drain v 40 input supply range fb = 0v, 4.5v < power input < 40v (note 4) %/v 0.04 0.06 line regulation +3.3v and +5v step-down controllers flyback/pwm controller internal regulator and reference oscillator and inputs/outputs downloaded from: http:///
m ax 7 9 7 h h igh-volt a ge , st e p-dow n cont rolle r w it h sync hronous re c t ifie r for cpu pow e r _______________________________________________________________________________________ 5 ___________________________________________________ ___________pin de sc ript ion dual mode is a trademark of maxim integrated products. rail-to-rail is a registered trademark of nippon motorola ltd. skip disables pulse-skipping mode when high. connect skip to gnd for normal use. do not leave unconnected. with skip grounded, the device automatically changes from pulse-skipping operation to full pwm operation when the load current exceeds approximately 30% of maximum. 16 dh high-side gate-drive output. dh normally drives the main buck switch. it is a floating driver output thatswings from lx to bst, riding on the lx switching-node voltage. 15 lx switching node (inductor) connection. lx can swing 2v below ground without hazard. 14 bst boost capacitor connection for high-side gate drive (0.1f) 13 dl low-side gate-drive output. dl normally drives the synchronous-rectifier mosfet. swings 0v to vl. name function 1 ss soft-start timing capacitor connection. ramp time to full current limit is approximately 1ms/nf. 2 pin 3 ref reference voltage output. bypass ref to gnd with 0.33f minimum. 7 fb feedback input. regulates at fb = ref (approximately 2.505v) in adjustable mode. fb is a dual mode tm input that also selects the fixed-output voltage settings as follows: connect to gnd for 3.3v operation. connect to vl for 5v operation. connect to a resistor divider for adjustable mode. fb can be driven with 5v rail-to-rail ? logic to change the output voltage under system control. 6 shdn shutdown control input, active low. logic threshold is set at approximately 1v (v th of an internal n-channel mosfet). tie shdn to v+ for automatic start-up. 5 sync oscillator synchronization and frequency select. tie sync to gnd or vl for 150khz operation; tie to ref for300khz operation. a high-to-low transition begins a new cycle. drive sync with 0v to 5v logic levels (see electrical characteristics for v ih and v il specifications). sync capture range is guaranteed to be 190khz to 340khz. 4 gnd low-noise analog ground and feedback reference point 12 pgnd power ground 11 vl 5v internal linear-regulator output. vl is also the supply-voltage rail for the chip. it is switched to the outputvoltage via csl (v csl > 4.5v) for automatic bootstrapping. bypass to gnd with 4.7f. vl can supply up to 5ma for external loads. 10 v+ battery voltage input (4.5v to 30v). bypass v+ to pgnd close to the ic with a 0.1f capacitor. conne cts to alinear regulator that powers vl. 9 csl current-sense input, low side. csl also serves as the feedback input in fixed-output modes. 8 csh current-sense input, high side. current-limit level is 100mv referred to csl. downloaded from: http:///
m ax 7 9 7 h _______________de t a ile d de sc ript ion the max797h is functionally identical to the max797.the only difference between the two devices is in the bst pins absolute maximum rating. the max797hs rating is 46v; the max797s rating is 36v. the higher rating allows the max797h to use a power input up to 40v, provided that the v+ pin is powered by a separate supply between 4.5v and 30v. circuit design and component selection for the max797h are identical to those for the max797; there - fore, such information is not included in this data sheet. refer to the max796/max797/max799 data sheet for design formulas and applications information. the applications information section in this data sheet con - tains suggestions for providing the 30v maximum v+supply input for the max797h when power input exceeds 30v. __________applic a t ions i nform a t ion pow e ring t he v + pin v+ can be supplied directly if a system supply between4.5v and 30v is available (see the typical operating circuit ). most of the max797hs internal blocks are sup - plied by vl, which uses v+ as its input. while the cur - rent into v+ is minimal, it depends heavily on the type of external mosfet used and the switching frequency: i gate = q g x f sw where q g is the sum of the high- and low-side mosfets total gate charges, and f sw is the switching frequency. furthermore, if the circuit output voltage oncsl exceeds the vl/csl switchover voltage, the max797h bootstraps itself (it connects vl to csl and turns off the linear regulator, supplying the ic from the circuit output), and v+ current is reduced to about 1a. if a 5v regulated supply is available, v+ and vl can be connected and fed from that supply (figure 1). in this mode, the vl regulator is bypassed. do not use this approach if the output voltage on csl can exceed the vl/csl switchover voltage. if a 5v regulated supply is not available, a linear regula - tor with a sufficient input voltage range can provide it (figure 2). this approach allows for a very wide input voltage range, which is useful if the circuit must run from several different power sources. the drawback of the linear regulator is the high quiescent current that these devices typically require, in addition to the current used by the feedback divider resistors (r1 and r2). for most applications, a better choice than figure 2s circuit takes advantage of the max797hs internal lin - ear regulator. there is no need to provide a regulated supply to v+, provided it is within the +4.5v to +30v v+ input voltage range. in figure 3, q1 is used to drop a 40v (max) input to 30v by dividing it by approximately 4/3. this approach results in a somewhat higher mini - mum input voltage than that of figure 2s circuit, but a much lower quiescent current than that of a linear regu - lator. if quiescent current must be minimized, an n-channel mosfet can be substituted for q1, and the divider-resistor values can be increased. powering v+ with a zener diode can be done in many different ways. the simplest is to use a standard shunt regulator to provide a regulated voltage in the 4.5v to 30v range (figure 4). resistor r1 must be chosen to allow the maximum required v+ current to be obtained from the minimum power input voltage. if the power input voltage varies appreciably, the result is higher- than-necessary input current from the highest power input voltage. an approach that reduces quiescent current is to use a zener diode as a dropping diode to keep v+ under 30v (figure 5). this results in a severely restricted minimum range for the power input voltage, which is not a problem for most high-voltage applica - tions. rl must be added to draw current and to ensure that there is sufficient forward drop across the zener diode if the max797h can be shut down or bootstrap off its output voltage. dut y-fa c t or lim it a t ions for low v ou t /v i n ra t ios the max797hs output voltage is adjustable down to2.5v (min). however, the combination of high input and low output voltages may not be possible at high switch - ing frequencies without introducing some amount of frequency instability. the minimum duty factor is deter - mined by delays through the error comparator, internal logic, gate drivers, and external mosfets. the delay is typically 425ns. with a switching period of 3.33 s (300khz), the minimum duty factor is 0.425 s / 3.33 s = 0.13. if v out / v in is less than this value, the ic will properly regulate the output voltage, but may extendthe period and switch at 150khz instead of 300khz. it may also alternate between these two frequencies. for example, if v in is 40v, the lowest v out that does not require less than the minimum duty factor is 40v x 0.13= 5.2v. below this output voltage, select the 150khz switching frequency (connect sync to vl or gnd). h igh-volt a ge , st e p-dow n cont rolle r w it h sync hronous re c t ifie r for cpu pow e r 6 _______________________________________________________________________________________ downloaded from: http:///
m ax 7 9 7 h h igh-volt a ge , st e p-dow n cont rolle r w it h sync hronous re c t ifie r for cpu pow e r _______________________________________________________________________________________ 7 figure 1. powering v+ and vl from a regulated +5v supply max797h shdn dh +3.3v output +4v to +40v power input bst lx dl pgnd csh csl ss ref sync gnd skip fb v+ +5v regulated supply vl similarly, at 150khz, the minimum duty factor is 0.425 s / 6.67s = 0.064. this means that duty factor is not an issue except at the maximum input voltage andminimum output voltage. for example, if v in is 40v, the lowest v out that does not require less than the minimum duty factor is 40v x 0.064 = 2.56v. if v out / v in is less than this value, the ic will properly regulate the output voltage, but may extend the period and switch at 75khz instead of 150khz. it may also alter - nate between these two frequencies. downloaded from: http:///
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied i n a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 ___________________m a x im i nt e gra t e d produc t s, 1 2 0 s a n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1997 maxim integrated products printed usa is a registered trademark of maxim integrated products. m ax 7 9 7 h h igh-volt a ge , st e p-dow n cont rolle r w it h sync hronous re c t ifie r for cpu pow e r ___________________chip i nform a t ion transistor count: 913 max797h shdn dh +7v to +40v input v+ vl out adj in r1 r2 max797h shdn dh up to +40v power input v+ vl r1 max797h shdn dh +20v to +40v power input 12v v+ vl r1 max797h shdn dh +8v to +40v power input 100k q1 300k v+ vl figure 2. powering v+ and vl with a +5v linear regulator figure 3. dividing the power input to supply v+ figure 4. powering v+ with a zener shunt regulator figure 5. powering v+ with a zener dropping diode downloaded from: http:///
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